Field of the Invention
The present invention relates in general to the field of semiconductors, and specifically to a semiconductor configuration and a method for fabricating a semiconductor configuration including a stacked cell with a protected barrier.
Conventional storage elements of semiconductor memory configurations usually use, as the storage dielectric, silicon dioxide or silicon nitride layers, although both of these have a dielectric constant in the region of merely about 6. A higher dielectric constant, however, would lead to a larger capacitance of the corresponding capacitor, so that the dimensions of the capacitor could actually be reduced if a corresponding increase in the capacitance is dispensed with.
In other words, the use of a dielectric having a large dielectric constant leads to a reduction in the area required for a capacitor with a corresponding capacitance, and thus to an increase in the integration level.
The developments practiced in this connection have yielded materials having a dielectric constant considerably higher than 6. Thus, an example of a paraelectric material that has been developed is (Ba.sub.x ST.sub.1-x)TiO.sub.3, "BST", which has a dielectric constant of the order of magnitude of 400. It is obvious that BST permits a considerable increase in the integration level when it is used instead of the customary silicon dioxide or silicon nitride layers.
Furthermore, conventional storage elements, such as, for example, a dynamic random memory (DRAM), use paraelectric materials, although these lose their charge, and consequently also the information stored with the charge, in the event of a supply voltage failure. Because of the leakage current that occurs in conventional storage elements of this type, the charge must be continually "refreshed" or rewritten to. The use of novel ferroelectric materials as a storage dielectric is desirable since this enables the fabrication of nonvolatile semiconductor memory configurations that do not lose their information in the event of a supply voltage failure and, in addition, do not have to be continually refreshed.
To summarize, the use of ferroelectric materials as a storage dielectric is intrinsically desirable in the case of semiconductor memory configurations, since it is then possible to achieve an increase in the integration level in conjunction with protection in respect to a supply voltage failure.
However, the practical realization of the use of such ferroelectric or else paraelectric materials in semiconductor memory configurations depends to a great extent on how these materials can be incorporated in an integrated semiconductor circuit configuration. Such ferroelectric or paraelectric materials that have been taken into consideration heretofore are, in addition to the BST already mentioned, (Pb,Zr)TiO.sub.3 (PZT), SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT), SrBi.sub.2 (Ta,Nb)O.sub.9 (SBTN) SrTiO.sub.3 (ST), ferroelectric and paraelectric polymers, etc. and generally ferroelectric and paraelectric materials.
Although these materials have high dielectric constants, and for this reason, are already used in ferroelectric random memories (FeRAM), their importance is still limited in practice. This is because it has been shown that the materials having a high dielectric constant cannot readily be used in semiconductor memory configurations. For example, the application of dielectric materials having a high dielectric constant or of ferroelectrics in large scale integrated stacked cells of semiconductor memory configurations is greatly impeded by the fact that the so-called "plug" or the filler material introduced into a contact hole is oxidized upon deposition of the dielectric. This oxidation takes place specifically because dielectrics having a high dielectric constant and ferroelectrics involve oxides which have to be exposed to high temperatures in an oxygen-containing atmosphere during the fabrication of the semiconductor or capacitor configuration.
Since the platinum electrode that is usually used for the capacitor contact is oxygen-permeable, the interface between the plug and the electrode, for example, oxidizes, which creates an electrical interruption.
FIG. 3 shows such a semiconductor configuration with a memory cell. In this semiconductor configuration, a dielectric insulator layer 2 made of silicon dioxide, for example, is applied to a semiconductor body 10 having a heavily doped region 9, and a hole 8 etched into the insulator layer. This hole 8 is filled with a filler material or plug 1 made from tungsten or polycrystalline silicon. Provided above the plug 1 is a barrier layer 3, which is made from, for example, WN, TiWN, TaN, WC, etc. The barrier layer 3 separates a lower electrode 5 made of platinum from the plug 1. A paraelectric or ferroelectric dielectric 6 is situated on the lower electrode 5, and an upper electrode 7 is applied in turn to the dielectric. In this semiconductor configuration, the barrier layer 3 is oxidized, beginning in the region 11, and this can ultimately lead to an electrical interruption. The oxidation advances from the region 11 along the interface 14 between the barrier layer 3 and the electrode 5 and along the interface 15 between the barrier layer 3 and the insulation layer 2.
This is a major reason that, in practice, the integration of a ferroelectric or paraelectric dielectric in a memory configuration in conjunction with a high integration level has been regarded heretofore as having little promise of success.
In an attempt to avoid significant oxidation of the interface between electrode and the plug, dielectrics having a high dielectric constant or ferroelectrics have previously been deposited in planar fashion above a LOCOS region only after the completion of a conventional CMOS transistor structure. In other words, besides a MOS transistor whose drain is connected, for example, to a bit line and whose gate is connected to a word line, a capacitor is provided above the LOCOS region. The upper electrode of the capacitor is made from platinum, for example, and is connected to the source electrode of a MOS transistor. The insulating layer of the capacitor is fabricated from a ferroelectric, and the second electrode (common plate), which is situated on a side of the ferroelectric opposite from the first electrode, is likewise fabricated from platinum, for example. SBT can be used as the dielectric. The sizes of the memory cells formed in this way are, for example, 10.1 .mu.m.times.16.5 .mu.m=167 .mu.m.sup.2 =46 F.sup.2, if a basic dimension of 1.9 .mu.m is used for F. In this case, the area of the capacitor is about 3.3 .mu.m.times.3.3 .mu.m=10.9 .mu.m.sup.2 =3 F.sup.2. In other words, there is a relatively large space requirement for the memory cell and/or the interconnection thereof to the capacitor.
The application of a capacitor above the LOCOS region has the advantage, however, that a sputtering or sol gel method can be used for fabricating the planar ferroelectric layer of the capacitor. In particular as a result of the application of the ferroelectric layer, which takes place in a greatly oxidizing environment, the diffusion of oxygen through the electrode, which is usually made from platinum, no longer impairs the layer situated underneath, since an oxide is already present there.
To summarize, although the deposition of a CMOS transistor structure above the LOCOS region is readily possible, it leads to a considerable reduction in the integration level.
Although it is possible for the ferroelectric layers to be applied directly above the electrically conductive plug, this leads to further oxidation and thus ultimately to insulation of the electrical connections.